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[Other resource] verilog SDRAM core

Description: 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
Platform: | Size: 28424 | Author: 于飞 | Hits:

[Other resource] 8051-core

Description: 8051单片机是一种应用最广泛的单片机.它的内核设计非常精简,这是用Verilog硬件描述语言写的8051单片机内核-8051 is a most widely used SCM. Its kernel design has been streamlined, This is used Verilog hardware description language to write the 8051 microcontroller core
Platform: | Size: 52196 | Author: 王二 | Hits:

[Other] SPI_Verilog

Description: SPI的verilog 核
Platform: | Size: 81010 | Author: tiangang1975@gmail.com | Hits:

[SCM] oc8051

Description: 51的VERILOG代码！适用于Xilinx的FPGA-51 VERILOG code! In Xilinx FPGA
Platform: | Size: 1220608 | Author: 林建加 | Hits:

[VHDL-FPGA-Verilog] usb1.1_Verilog

Description: usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
Platform: | Size: 131072 | Author: 李恒 | Hits:

[VHDL-FPGA-Verilog] t80

Description: Configurable cpu core that supports Z80, 8080 and gameboy instruction sets
Platform: | Size: 41984 | Author: 吴毅 | Hits:

[VHDL-FPGA-Verilog] video_from_opencore

Description: 全电视信号编码器，verilog的，看看有借鉴价值否？-video signal encoder, Verilog, to see whether the reference value?
Platform: | Size: 152576 | Author: 12 | Hits:

[Crack Hack] aes_core

Description: AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
Platform: | Size: 79872 | Author: | Hits:

[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 35840 | Author: 戴鹏 | Hits:

[ARM-PowerPC-ColdFire-MIPS] AUDIO_DAC

Description: 一个关于声音处理的Verilog语言编写的解码芯片，可以用于FPGA处理芯片的IP核，欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
Platform: | Size: 2048 | Author: 赵春生 | Hits:

[VHDL-FPGA-Verilog] VerilogHDLICdesign

Description: 精通VerilogHDL：IC设计核心技术实例详解-proficient VerilogHDL : IC design example explanation of the core technology
Platform: | Size: 521216 | Author: haha | Hits:

[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206848 | Author: 张清平 | Hits:

[Other] PCI_Target_ip

Description: pci core altera fpga pci开发设计资料-pci core altera fpga development of design information pci
Platform: | Size: 428032 | Author: zhouhong | Hits:

[VHDL-FPGA-Verilog] adma

Description: Wishbone dma ip core
Platform: | Size: 7168 | Author: liwen | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[ARM-PowerPC-ColdFire-MIPS] arm7_core_verilog

Description: arm7timi架构的verilog代码，可以仿真，通过学习，可以掌握arm7内部架构。-arm7timi verilog structure of the code can be simulated, through learning, be able arm7 internal structure.
Platform: | Size: 677888 | Author: blueli | Hits:

[VHDL-FPGA-Verilog] my_ip_core

Description: 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
Platform: | Size: 51200 | Author: 刘海 | Hits:

[VHDL-FPGA-Verilog] cpu86model

Description: 关于8086的软核fpga代码，可以直接再fpag的开发板上调试，好用而且是免费的-on the 8086 soft-core fpga code can then direct the development fpag board debugging, handy and free
Platform: | Size: 270336 | Author: 赵春生 | Hits:

[VHDL-FPGA-Verilog] VGA_LCD_IP

Description: vga ipcore的verilog代码
Platform: | Size: 495616 | Author: | Hits:

[VHDL-FPGA-Verilog] vspi

Description: verilog VSIP core,用verilog语言编写，希望对各位朋友有所帮助！-verilog VSIP core, using Verilog language, and they hope to help all our friends!
Platform: | Size: 13312 | Author: liuzinan | Hits:
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